DRAM Principal Design Verification Engineer
Core
Lead digital verification methodology and infrastructure development for next-generation DRAM products, driving scalable testbench architectures and AI-powered verification solutions.
Role type
Principal Design Verification Engineer (Technical Leader)
Builds
Scalable UVM-based verification environments, reusable verification IP, and automation solutions for DRAM silicon.
Domain
Semiconductor / Memory (DRAM)
Required skills
System Verilog, UVM, constrained-random verification, functional coverage, assertion-based verification, gate-level simulation, VLSI circuit design fundamentals, technical leadership, mentoring
Preferred skills
Memory product experience (DRAM, LPDDR, GDDR, HBM), analog or mixed-signal verification, Python programming (OOP), AI/ML application to verification workflows, organization-wide technology adoption
Technologies
UVM, System Verilog, Python, gate-level simulators
Responsibilities
Lead digital verification methodology and infrastructure development; Architect scalable UVM-based verification environments and reusable IP; Drive verification planning, coverage closure, and silicon quality; Innovate with AI-driven verification and intelligent automation; Partner with cross-functional teams to accelerate product development; Mentor engineers and influence verification best practices
Seniority
Principal, hands-on IC with mentorship
