Pre-Silicon Digital Verification Engineer
Core
Verifying complex digital IP blocks for mixed signal integrated circuits to ensure bug-free designs on the first tapeout.
Role type
Pre-silicon digital verification engineer (mixed signal ASIC)
Builds
Verification testbenches, testcases, and verification environments for digital control blocks
Domain
Semiconductor / Mixed Signal ASIC Design
Required skills
System Verilog, UVM, Formal Verification, Constrained Random Verification, Code Coverage Analysis, Debugging, Specification Development
Preferred skills
Object-Oriented Programming, Clock Domain Crossing Verification, Analog Circuit Design, Digital Design & Computer Architecture
Technologies
System Verilog, UVM, Formal Verification Tools, Mixed Signal Simulation Tools
Responsibilities
Collaborate in developing precise design specifications for digital control blocks; Create block and chip level verification plans; Architect and create block level verification elements; Use System Verilog and UVM to develop drivers, tests, reference models and checkers; Debug test failures and work with designers to develop fixes; Use functional and code coverage to track progress and gauge tapeout readiness.
Seniority
Mid-level IC Engineer
