Senior Staff - Design Verification Engineer
Core
Lead definition and execution of scalable, reusable, and high-quality verification strategies for next-generation SoCs targeting AI, HPC, and Networking applications.
Role type
Senior Staff Design Verification Engineer (SoC)
Builds
Reusable, modular, and portable verification platforms for large-scale SoCs
Domain
Semiconductor / SoC Design Verification
Deliverable
production ML models
Required skills
SystemVerilog, UVM, Coverage-driven verification, Assertion-based verification (SVA), Portable Stimulus (PSS), SoC architecture, Multi-IP integration, High-speed interfaces, Debugging
Preferred skills
AI/ML in verification workflows, Emulation/prototyping, Performance verification, Power-aware verification, Cross-level stimulus reuse
Technologies
SystemVerilog, UVM, PSS, PCIe, Ethernet, CXL, UCIe
Responsibilities
Define overall verification architecture for large-scale SoCs; Architect reusable verification platforms; Establish methodologies for seamless reuse and portability; Lead development of high-performance, coverage-driven testbenches; Drive multi-level verification strategies; Define verification quality metrics and coverage closure strategies; Champion fail-fast philosophy; Drive initiatives toward first-pass silicon success; Leverage AI/ML techniques to automate testbench generation and improve coverage; Mentor DV teams on best practices and methodology adoption.
Seniority
Senior Staff, hands-on IC with strategic scope
