Principal Physical Verification Engineer
Core
Execute chip-level physical verification (DRC, LVS, ERC, PERC) and resolve issues for advanced node ASICs (3nm/2nm) and 2.5D/3D chiplet integration.
Role type
Principal Physical Verification Engineer
Builds
Custom high-performance ASICs for AI/ML ecosystems and networking infrastructure
Domain
Semiconductor / ASIC Physical Design
Required skills
Physical verification (DRC, LVS, ERC, PERC), EDA tools (ICV, Calibre, Pegasus), Rule deck coding, Python/Tcl/Perl scripting, DFM/Critical Area Analysis, Floorplan/I/O/Bump planning
Preferred skills
Silicon tape-out experience, RTO tapeout experience, ESD/Latch-up analysis, Automated dummy metal/fill strategies, Collaboration with P&R teams
Technologies
ICV, Calibre, Pegasus, Python, Tcl, Perl
Responsibilities
Execute chip-level physical verification and issue resolution; Set up DRM runsets for advanced nodes; Manage top-level floorplan, I/O, and bump planning rules; Resolve physical design issues related to chip integration and assembly; Provide technical direction on verification methodologies; Develop best practice guidelines for verification flows
Seniority
Principal, hands-on IC
