ASIC Design Verification Engineer I (Full Time) - United States
Core
Develop and verify ASICs for Cisco's core Switching, Routing, and Wireless products using simulation, emulation, and bring-up processes.
Role type
ASIC Design Verification Engineer
Builds
Hardware platforms for data center solutions
Domain
Semiconductor / ASIC Design Verification
Required skills
System Verilog, UVM methodology, Perl scripting, Python scripting, test bench construction, functional coverage, regression debugging
Preferred skills
Complex block/cluster verification, constrained random environments, SoC top-level verification, Veloce/HAPS emulation, SystemVerilog constraints and classes
Technologies
System Verilog, UVM, Perl, Python, Veloce, HAPS
Responsibilities
Maintain and enhance existing DV environments, construct test benches with scoreboards/agents/sequencers, write test plans and develop test cases, debug regression failures, ensure verification coverage
Seniority
Entry-level to Mid-level IC
