Verification Engineer, Senior
Core
Senior ASIC verification engineer defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP (block/SoC) for high-performance, low-power products.
Role type
Senior IC ASIC verification engineer
Builds
High-performance, high-quality, low-power world-class products (ASICs/SoCs)
Domain
Semiconductor / ASIC Design / Digital & Analog Mixed Signal
Required skills
SystemVerilog, UVM, constrained random verification, SerDes PHY verification, analog mixed signal verification, formal verification, gate level simulation, power aware UPF verification, Python, Perl, C/C++, GNU Make
Preferred skills
Ethernet and PCIe standards knowledge, third-party VIP integration, post-silicon chip bringup
Technologies
SystemVerilog, UVM, Python, Perl, C/C++, GNU Make, MATLAB, Ethernet, PCIe
Responsibilities
Review digital design specifications and devise verification plans; Develop testbenches and test cases using SystemVerilog and UVM; Debug simulations by identifying root causes; Integrate analog behavioral models into verification environments; Collaborate with Design, Systems, Firmware, and Analog teams; Facilitate bit-matching between RTL designs and MATLAB system models; Integrate third-party VIPs for compliance testing; Lead, plan, and coordinate tasks with team members
Seniority
Senior, hands-on IC
