Sr . Principal Verification Engr
Core
Lead end-to-end pre-silicon System-on-Chip (SoC) verification, developing robust verification environments and driving silicon readiness.
Role type
Senior Principal Verification Engineer (SoC)
Builds
Pre-silicon SoC verification environments and strategies
Domain
Semiconductor / Hardware Verification
Required skills
UVM, SystemVerilog, Verilog, C, RTL analysis, constrained-random stimulus, low power verification (CPF/UPF), netlist verification, hardware-software co-verification, verification planning, team leadership, methodology improvement
Preferred skills
Digital design knowledge, best practices in verification
Technologies
UVM, SystemVerilog, Verilog, C, CPF, UPF
Responsibilities
Lead pre-silicon SoC verification activities end-to-end; Define and execute SoC-level verification strategies and plans; Develop and maintain UVM based verification environments; Create verification plans from architectural requirements; Perform low power intent verification using CPF, UPF; Conduct netlist verification; Execute hardware-software verification; Plan and track verification tasks to ensure silicon tape out readiness; Define tasks for team members to meet project timelines; Lead and mentor verification engineers; Drive verification methodology improvements; Collaborate with architecture, RTL design and firmware teams.
