Package Layout Engineer
Core
Design IC package substrate layouts for standard and advanced packaging technologies, supporting package architecture from concept through development.
Role type
Package Layout Design Engineer
Builds
IC package substrates and layouts for AI/HPC workloads
Domain
Semiconductor packaging, signal integrity, power integrity
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
IC package layout design, substrate stack-up optimization, DFM/DFA implementation, signal integrity analysis, power integrity analysis, analog/digital interface design, Allegro X APD proficiency
Preferred skills
Cadence Integrity 3DIC familiarity, layout tool scripting (SKILL/Python), multi-chiplet architecture knowledge, floorplan evaluation, escape routing design, bump pattern design
Technologies
Allegro X APD, Cadence Integrity 3DIC, Expedition Package Designer, Pads Layout, Altium
Responsibilities
Deliver IC package substrate layouts for standard and advanced packaging technologies; Contribute to product concept phase by delivering preliminary substrate designs and floorplanning; Collaborate with substrate suppliers and OSATs to apply layout design rules and guidelines; Generate fab files and coordinate with suppliers for DFM/DFA closure; Design packages adhering to signal, power, thermal, and mechanical requirements; Support signal/power integrity engineers with iterative test routes; Coordinate across teams to execute Package Design Tape Outs; Support design automation and verification activities
Seniority
Mid-Senior, hands-on IC
