[2027 Internship] Standard Cell Library Design Engineer Intern
Core
Design and characterize standard cell libraries for leading-edge process nodes (7nm/5nm/4nm/3nm) to establish design platforms for MediaTek projects.
Role type
Standard Cell Library Design Engineer Intern
Builds
Standard cell libraries for advanced technology nodes
Domain
Semiconductor / Digital IC Design
Required skills
Timing modeling, Power analysis, Constraint analysis, Noise modeling, Variation analysis, Flow development, Testchip design, Si data analysis, Big data processing, Data visualization
Responsibilities
Setup design platform for MediaTek projects, Perform timing/power/constraint/noise/variation modeling and analysis, Develop flow for >15K logic circuits, Design testchips and develop Si data analysis flow
Seniority
Intern
