[2027 Internship] Custom IC Layout Engineer Intern
Core
Design and implement custom integrated circuits (ICs) from scratch, focusing on physical design (layout) for Foundation IP, Analog IP, or RFIC using CMOS technology.
Role type
Custom IC Layout Engineer Intern
Builds
Custom IC layouts (Foundation IP, Analog IP, RFIC)
Domain
Semiconductor / Integrated Circuit Design
Required skills
Physical Design (Layout), Floor-planning, Device placement, Signal routing, Debugging, EDA tools (Cadence, Synopsys, Siemens), PPA optimization
Technologies
Cadence, Synopsys, Siemens, CMOS
