Principal Analog Design Engineer — Mixed-Signal PHY (Clocking / High-Speed I/O)
Core
Design and validate custom analog circuits for high-speed clocking (PLL, DLL, CDR) and transmitter/receiver components in chip-to-chip and memory interconnect PHYs.
Role type
Principal Analog Design Engineer (Mixed-Signal PHY)
Builds
Custom analog circuits for high-speed signaling and memory interconnects
Domain
Semiconductor / High-Speed Interface / Mixed-Signal IC Design
Deliverable
production ML models | product features
Required skills
Transistor-level analog circuit design, PLL/DLL/CDR architecture, HSpice simulation, Process corner/Monte Carlo analysis, Jitter analysis, Post-silicon characterization
Preferred skills
High-speed transmitter development (pre-emphasis, impedance matching), Receiver development (CTLE/DFE, sense amplifiers), Die-to-die PHY architectures (UCIe, AIB), OTP/fuse calibration, AI/ML tool usage
Technologies
HSpice, CMOS nodes, UCIe, AIB, BoW
Responsibilities
Lead development of specialized analog components for clocking and SerDes; Define top-level PHY analog architecture and signal chain partitioning; Build transistor-level simulation testbenches for yield sensitivity; Define interface specifications between analog blocks and digital wrappers; Collaborate with layout teams for custom analog layout and post-silicon lab characterization
Seniority
Principal, hands-on IC design with strategic architecture ownership