Staff Engineer, IP Dev Layout
Core
Design and development of critical analog, mixed-signal, custom digital blocks, and full chip level integration support for memory and storage solutions.
Role type
Staff Engineer, IP Dev Layout
Builds
Block-level layouts for analog/mixed-signal/custom digital blocks (Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier)
Domain
Semiconductor / VLSI / Analog & Mixed-Signal Design
Required skills
Analog/custom layout build in advanced CMOS process, Cadence VLE/VXL, Mentor Graphic Calibre DRC/LVS, Analog Layout fundamentals (Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop), Layout effects on circuit (speed, capacitance, power, area), Build constraints implementation, Build hierarchy and Memory design architectures, Physical verification of custom layout
Preferred skills
Multiple Tape out support, AI-related tools usage
Technologies
Cadence VLE, Cadence VXL, Mentor Graphic Calibre
Responsibilities
Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support; Perform layout verification like LVS/DRC/Antenna, quality check and support documentation; Responsible for on-time delivery of block-level layouts with acceptable quality; Demonstrate leadership skills in planning, area/time estimation, scheduling, and execution; Contribute to effective project-management; Effectively communicating with Global engineering teams
Seniority
Senior, hands-on IC