Lead Analog Layout Design Engineer
Core
Lead Technical Designer for high-speed SERDES analog/mixed-signal layouts in UCIe products up to 64 Gbps on leading-edge nodes (e.g., 2nm FinFET CMOS).
Role type
Lead Analog Layout Design Engineer (SERDES/UCIe)
Builds
High-speed SERDES IP blocks and PHY top-level integrations for UCIe products
Domain
Semiconductor IC Design / Analog Mixed-Signal / High-Speed I/O
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
High-speed SERDES layout design, Analog/mixed-signal circuit layout, Floor planning, Foundry design rule verification, Block-level to PHY integration, Driver/Receiver/Serializer/Deserializer design, PLL design, Clock distribution, Bias/Bandgap design, Voltage regulator design
Preferred skills
Cadence Virtuoso tool expertise, Sub-16nm technology experience, Tool development collaboration, Analog design paradigm innovation
Technologies
Virtuoso, PVS, 2nm FinFET CMOS, 64 Gbps SERDES
Responsibilities
Design high-speed SERDES layouts for UCIe products, Execute back-end flow from floor planning to final verification, Lead technical aspects of layout design from block to PHY level, Collaborate with global circuit designers and project managers, Participate in layout tool development with R&D teams
Seniority
Senior, hands-on IC
