Principal Package Design Engineer
Core
Lead the design, development, and qualification of next-generation advanced semiconductor packaging solutions for high-performance chips and electronic products.
Role type
Principal IC packaging engineer (advanced packaging)
Builds
Advanced semiconductor packages (Flip-chip, WLP, SiP, 2.5D/3D, heterogeneous bonding) for AI infrastructure, data center power management, and high-performance computing.
Domain
Semiconductor / Advanced Packaging / Power Electronics
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Advanced package architecture design, thermal and mechanical simulation, failure analysis, OSAT/vendor strategy, DFM, cross-functional technical leadership
Preferred skills
Power semiconductor packaging (Si/SiC/GaN), chiplet-based packaging, W2W/D2W/D2D heterogeneous integration, JEDEC/IPC standards knowledge
Technologies
Cadence Allegro, SolidWorks, ANSYS, COMSOL, JMP, Minitab
Responsibilities
Define package architecture based on electrical/thermal/mechanical requirements; perform signal integrity, thermal, and mechanical stress simulations; drive OSAT selection and assembly flow development; lead qualification activities (DOE, failure analysis); resolve yield and manufacturing issues; mentor junior engineers
Seniority
Principal, hands-on IC with strategy & mentorship