Sr. Digital Implementation Engineer
Core
Creating turn-key solutions for Cellular IoT devices by owning netlist delivery to Physical Design and ensuring RTL database integrity.
Role type
Senior IC digital implementation engineer (ASIC synthesis)
Builds
ASIC chips for Cellular IoT devices
Domain
Semiconductor / Embedded Systems / IoT
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ASIC synthesis flow, STA/DFT, IP integration, UPF power intent, Verilog/SystemVerilog, Tcl, Perl, Python, timing closure, constraint generation/validation
Preferred skills
Design Compiler, Genus, IP integration, BIST, Clock Domain Crossing (CDC) analysis, deep submicron tapeout, OCV, noise, crosstalk, IR-drop
Technologies
Cadence, Tessent, Design Compiler, Genus
Responsibilities
Run complete synthesis flow, Define and document synthesis methodology and scripts, Manage UPF flow for power intent, Perform RTL and Netlist hand-off checks (LEC), Interface with Physical Design for floor-planning and timing closure, Analyze STA results and facilitate RTL changes and Timing ECOs
Seniority
Senior, hands-on IC
