ASIC/SOC CAD Engineer
Core
Develop, maintain, and improve Physical Design CAD flow and infrastructure to produce performant silicon for high-performance GenAI products.
Role type
Senior IC ASIC/SOC Physical Design CAD Engineer
Builds
High-performance and sustainable GenAI silicon across compute, memory management, and high-speed connectivity
Domain
Semiconductor / ASIC Physical Design / GenAI
Deliverable
production ML models
Required skills
Perl, Python, TCL, RTL to GDSII flow construction, sign-off, EDA tool selection and deployment, license management, job scheduler optimization, front-end CAD support
Preferred skills
EDA license management, LSF, cloud-based silicon development
Technologies
Perl, Python, TCL, EDA tools
Responsibilities
Develop and maintain Physical Design flow from RTL to GDSII, automate back-end runs and generate metrics, evaluate and deploy EDA tools, work with vendors to drive tool enhancements, train and support flow users, manage licenses and compute resources
Seniority
Senior, hands-on IC
