IP Logic Design Engineer - Advanced Technologies Group
Core
Develop and implement RTL micro-architecture for next-generation PHY designs, collaborating with architecture, analog, CAD, and timing teams to deliver elite physical layer solutions.
Role type
Senior IC IP Logic Design Engineer (PHY)
Builds
Next-generation PHY designs and SoC developments
Domain
Semiconductor / Analog & Mixed-Signal (AMS) / Physical Design
Required skills
RTL implementation, Micro-architecture design, AMS PHY development, ASIC verification flows, System Verilog, Verilog, C/C++, Perl/Tcl scripting, STA methodology, GDS implementation, Design verification
Preferred skills
CAD and design methodologies, Debugging at PHY level, Industry standard interfaces knowledge
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