ASIC/SOC Silicon Physical Design Engineer
Core
Developing performant and functionally correct silicon for high-performance and sustainable GenAI across compute, memory management, and high-speed connectivity.
Role type
Senior IC ASIC/SOC Silicon Physical Design Engineer
Builds
Best-in-class silicon for MatX products
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
ASIC Physical Design, RTL to GDSII flow, partitioning, floorplanning, synthesis, place & route, clocking, sign-off (equivalency, extraction, timing, power estimation, EMIR, physical verification), Perl, Python, TCL
Preferred skills
Third-party Design Services partner experience
Technologies
Perl, Python, TCL
Responsibilities
Contribute to Physical Design methodology for scalable block, subsystem, and fullchip designs; Own subsystems or chip-level Physical Design deliverables; Plan and drive intermediate and sign-off reviews; Collaborate with Design, DFT, and co-owners to optimize designs for PPA.
Seniority
Senior, hands-on IC
