Principal Design Engineer
Core
Supporting integration, customization, and post-silicon bring-up of CDNS DDR IP subsystems for customers.
Role type
Principal Design Engineer (DDR IP)
Builds
DDR Controller and PHY SOC integrations
Domain
Semiconductor / Memory Interface Design
Required skills
DDR4/5 and LPDDR4/5 IP knowledge, DDR protocol design/verification, AMBA protocols (AXI, AHB, APB), RTL and gate-level simulation, timing closure, IC implementation tools, Cadence tools, Lint/CDC, Static Timing Analysis
Preferred skills
Silicon bring-up/testing experience, SOC-level integration experience
Technologies
Cadence tools, DDR4/5, LPDDR4/5, AXI, AHB, APB
Responsibilities
Analyze and resolve complex subsystem application or implementation issues, Support DDR Controller and PHY SOC integration reviews, Perform RTL and gate level simulations to verify functionality, Assist customers with gate level simulations and timing closure, Participate in development of CDNS documentations and checklists for customers, Support post silicon bring-up and deployment activities by our customers
Seniority
Principal, hands-on IC design and client support
