版图设计工程师（深圳） - 芯片研发
Core
Designing layout for custom hardware blocks to optimize performance and reduce costs for ByteDance's business scenarios.
Role type
Senior IC layout engineer (advanced process nodes)
Builds
Custom hardware blocks for cloud and business-specific chips
Domain
Semiconductor chip design (advanced process nodes)
Required skills
Layout design for advanced process nodes (7nm and below), DRC/LVS/ERC verification, parasitic RC optimization, EMIR optimization, high-speed circuit layout, memory layout, standard cell customization, Cadence, Synopsys, Mentor tools
Technologies
Cadence, Synopsys, Mentor
Responsibilities
Complete layout work for specific blocks in collaboration with circuit design engineers, independently perform DRC/LVS/ERC verification, optimize layout to reduce parasitic RC and improve EMIR, communicate with circuit design engineers to ensure layout meets design requirements
Seniority
Senior, hands-on IC