模拟IP K库工程师（芯片平台） - 芯片研发
Core
Deliver timing and power libraries (CCS/LVF/CMM/APL/Verilog) for analog/mixed-signal IPs including PLLs, LDOs, power switches, decaps, and high-speed interfaces (SerDes/UCIe) across the chip design flow.
Role type
Senior IC analog/mixed-signal library engineer
Builds
Design kits and library models for analog/mixed-signal IPs
Domain
Semiconductor IC design, analog/mixed-signal
Required skills
Analog/mixed-signal circuit understanding, SPICE simulation (HSPICE/Spectre/FineSim), Python/Shell/Tcl scripting, Liberty format expertise, timing/power model knowledge (CCS/NLDM/LVF/APL/PGV/CMM), EDA tool usage (NanoTime/Liberate AMS)
Preferred skills
Advanced process node experience, Foundry PDK knowledge, IR/EM analysis tools (RedHawk/Voltus), high-speed interface modeling (SerDes/UCIe/DDR), AI/Agent automation interest
Technologies
NanoTime, Liberate AMS, HSPICE, Spectre, FineSim, Python, Shell, Tcl, Liberty, CCS, NLDM, LVF, APL, PGV, CMM, RedHawk, Voltus
Responsibilities
Extract timing and power parameters using EDA tools or custom scripts; generate fake libs and design kits; collaborate with analog/SYN/STA/PD teams to clarify interface and constraint requirements; automate library generation and version management
Seniority
Mid-level, hands-on IC
