Staff Engineer Mixed Signal Layout (f/m/div.)
Core
Execute full-custom IC and block-level layout from schematic to tape-out for high-frequency RF blocks and high-speed SerDes components.
Role type
Staff engineer mixed-signal layout
Builds
High-frequency RF ICs and high-speed SerDes chips
Domain
Semiconductor / Analog & RF IC design
Required skills
Full-custom IC layout, CMOS and FinFET technologies, high-speed SerDes interfaces, DRC/LVS/ERC verification, parasitic extraction and management, floorplanning, ESD/latch-up/EM guidelines, EDA tools (Cadence Virtuoso, Siemens Calibre), technical leadership, mentoring
Technologies
Cadence Virtuoso, Siemens Calibre
Responsibilities
Execute full-custom layout from schematic to tape-out, implement matching and isolation strategies, run physical verification (DRC, LVS, ERC), analyze and minimize parasitics, perform floorplanning and pad-ring assembly, lead and mentor junior layout engineers
Seniority
Staff, hands-on IC design with leadership
