版图设计工程师（芯片平台） - 芯片研发
Core
Designing physical layouts for chip blocks within a unified platform covering logic synthesis to mass production, supporting multi-process and multi-project automated flows.
Role type
Senior IC physical design engineer (chip platform)
Builds
Chip layouts for logic, memory, and standard cells across multiple process nodes
Domain
Semiconductor / Chip Design
Required skills
Layout design for advanced nodes (7nm and below), DRC/LVS/ERC verification, parasitic RC optimization, EMIR optimization, high-speed circuit layout, memory layout, standard cell customization, Cadence, Synopsys, Mentor tools
Preferred skills
None stated
Technologies
Cadence, Synopsys, Mentor
Responsibilities
Collaborate with circuit designers to complete block layouts, independently perform DRC/LVS/ERC verification, optimize layouts to reduce parasitic RC and improve EMIR, communicate with circuit designers to ensure layout requirements are met
Seniority
Senior, hands-on IC
