ADDA/模拟信号链设计工程师（存算与AI） - 芯片研发
Core
Design high-efficiency AI chips using in-memory computing architectures to overcome the 'memory wall' bottleneck, focusing on ADC/DAC and analog signal chain IP for AI large model applications.
Role type
Senior IC analog/mixed-signal engineer (ADC/DAC/AFE)
Builds
High-efficiency AI chips and analog signal chain IPs
Domain
Semiconductor / AI computing / Analog circuit design
Deliverable
production ML models
Required skills
ADC/DAC architecture and design, analog signal chain modeling (MATLAB/VerilogA), noise/linearity/power analysis, Cadence Virtuoso/Spectre/HSPICE, layout awareness, tape-out debugging
Preferred skills
High-performance AFE/Buffer design, VerilogAMS/XA simulation, Python/TCL automation scripting
Responsibilities
Define architecture and specs for ADC/DAC and analog signal chain IPs; design and optimize high-efficiency ADC/DAC and front-end modules; perform system-level modeling and simulation; conduct post-tape-out testing, analysis, and design revisions; collaborate on SoC integration and bring-up
Seniority
Senior, hands-on IC
