版图设计工程师（西安） - 芯片研发
Core
Layout design engineer for custom hardware optimization in cloud chips, collaborating with circuit designers to create reliable layouts for advanced semiconductor processes.
Role type
Senior IC layout engineer (analog/digital mixed-signal)
Builds
Custom hardware for ByteDance business scenarios, including cloud chips and specialized accelerators
Domain
Semiconductor / Chip Design / Hardware
Required skills
Layout design for 7nm and below processes, DRC/LVS/ERC verification, parasitic RC optimization, EMIR optimization, high-speed circuit layout, memory layout, standard cell customization, Cadence Virtuoso, Synopsys IC Validator, Mentor Calibre
Preferred skills
Experience with ByteDance's internal chip projects, cross-functional collaboration with circuit design teams
Technologies
Cadence Virtuoso, Synopsys IC Validator, Mentor Calibre, 7nm process nodes
Responsibilities
Complete layout work for specific blocks in collaboration with circuit designers, independently perform DRC/LVS/ERC verification, optimize layouts to reduce parasitic RC and improve EMIR, communicate with circuit designers to ensure layout requirements are met
Seniority
Senior, hands-on IC