IC Layout Engineer
Core
Analyze the physical design, layout, and manufacturing implementation of leading-edge integrated circuits (AI/datacenter hardware) to derive architectural and competitive insights.
Role type
IC Layout Engineer (Technical Analysis)
Builds
Competitive intelligence reports, technical research publications, and strategic insights on hardware design choices.
Domain
Semiconductor industry, AI hardware, Datacenter hardware
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
IC layout analysis, physical design flows (floorplanning, placement, CTS, routing), standard-cell architecture knowledge, analog/mixed-signal layout interpretation, semiconductor sample preparation, analytical tool operation (FIB, SEM, X-ray), DTCO/STCO reasoning, technical writing
Preferred skills
P&R and custom layout tools (Innovus, Fusion Compiler, Virtuoso), GDS/OASIS reading, advanced packaging knowledge, Python for data analysis, electrical failure analysis experience, statistical process control literacy
Technologies
FIB, SEM, X-ray, GDS, OASIS, Innovus, Fusion Compiler, Virtuoso, Python
Responsibilities
Conduct detailed physical design and layout analysis of AI/datacenter hardware; Perform digital and analog floorplan analysis; Assess standard-cell library choices and optimization strategies; Analyze analog/mixed-signal layout regions; Drive end-to-end teardown and characterization; Identify competitive advantages and generational changes; Co-author technical research.
Seniority
Mid-level to Senior (2+ years experience preferred)