封装设计工程师（存算与AI） - 芯片研发
Core
Lead high-bandwidth memory packaging design and optimization for AI chips, focusing on TSV, Microbump, and Interposer designs to enable high-efficiency computing.
Role type
Senior IC packaging design engineer (3D/2.5D advanced packaging)
Builds
High-efficiency AI chips based on in-memory computing architectures
Domain
Semiconductor industry + Advanced packaging (3D/2.5D, HBM, TSV)
Deliverable
production ML models
Required skills
TSV design, Microbump design, Interposer design, 3D/2.5D packaging design, Co-Design (chip-packaging), DRC/LVS verification, JEDEC HBM standards knowledge, thermal management, stress matching
Preferred skills
Large-scale substrate design, end-side FOPOP packaging, 3DICC tool proficiency, Mentor Xpedition proficiency, Cadence APD/SiP proficiency
Technologies
TSV, Microbump, Interposer, CoWoS, InFO, HBM, 3DICC, Cadence APD/SiP, Mentor Xpedition
Responsibilities
Lead high-bandwidth memory packaging design and optimization; Participate in chip-packaging co-design; Independently design and mass-produce large-scale substrates or end-side FOPOP packages; Develop 3D/2.5D advanced packaging technologies; Collaborate with chip design, process, and test teams.
Seniority
Senior, hands-on IC
