Analog IC Design
1,386 open positions
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Senior Designer, Layout↗ Analog DevicesValencia, VC, ES 12d Create high-performance edge processing solutions for hearables and wearables by independently designing complex integrated circuit layouts and optimizing process flows.
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Semi-conductor Engineer↗ Topscience (s) Pte LtdSingapore, S00, SG 12d Design and develop integrated circuit layouts, manage manufacturing processes, and develop test programs to ensure product performance.
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Principal Signal Integrity Engineer MicronBoise, ID - Main Site, US 12d Principal Signal Integrity Engineer developing energy-efficient bandwidth solutions for high-speed memory and die-to-die interfaces via original analysis, modeling, and simulation.
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Advanced Package Technology Engineer BroadcomUSA-Colorado-Fort Collins-4380 Ziegler Road 12d Developing cost-effective, high-performance advanced custom package solutions (2.5D/3D) for ASIC products, ensuring signal integrity, thermal, and structural reliability.
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Principal Engineer - HIG HBM - ARCHITECTURE↗ Micron TechnologyRichardson, TX, US 12d Define and drive the architecture of high-speed analog and mixed-signal IO subsystems for next-generation High Bandwidth Memory (HBM) products used in AI and high-performance computing.
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Design Engineer SilabsOslo 12d Architect, design, and verify analog and digital circuits for low-power IoT MCUs and wireless transceivers.
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Principal SerDes Design Engineer↗ Celero CommunicationsRemote, US $200k–$200k12d Architecting and designing high-speed SerDes for next-generation transceivers to power AI systems.
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Analog Design, Manager - 18463↗ SynopsysKanata, ON, CA $142k–$142k13d Lead a team of engineers in designing high-speed Multi-Gbps SerDes IP (NRZ/PAM4) for next-gen SoCs, focusing on transistor-level analog circuit architecture and system budgeting.
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Principal Product Development Engineer CommScopeBelgië 13d Lead ideation and design of next-generation optical interconnect technology solutions for high-speed, high-density data center platforms.
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Principal Analog Mixed-Signal Design Engineer AsteralabsSan Jose $207k–$207k14d Architect and design high-performance analog and mixed-signal circuits for SerDes, PHY, and high-speed I/O to enable rack-scale AI infrastructure.
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Principal Electrical Engineer Renesas-ElectronicsChandler, Arizona, us 14d Lead ESD architecture development, IP design, and sign-off verification for advanced-node semiconductor products including FinFET technologies and high-speed interfaces.
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Master - Elektro- und Informationstechnik Analog Chipdesign AumovioRegensburg, BY, de 15d Develop analog and mixed-signal integrated circuits for future mobility solutions, specifically for automotive applications.
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Sr Staff/Principal Laser Design Engineer LightmatterBoston, MA $212k–$212k15d Design high-power laser epitaxial structures and devices (DFB, DBR, external-cavity) for AI data center photonics.
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Analog Mixed-Signal IC Design Engineer (Custom Digital Timing Characterization and Liberty Modeling) – TeraWave BlueoriginSan Diego, CA, US $230k–$230k15d Develop, simulate, characterize, and deliver Liberty (.lib) timing models for custom analog-digital interface circuits used in complex integrated circuits.
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Systems Engineering Intern - MS/PhD Texas InstrumentsDallas, TX, United States 15d Develop advanced analog and digital chips and system products from concept to mass production, defining product roadmaps and negotiating trade-offs with stakeholders.
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ADCE Packaging Design Architect IntelUS, Arizona, Phoenix $221k–$312k15d Drives end-to-end substrate design from concept through tape out, implementing physical layout and routing to optimize silicon-package-board performance.
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ASIC Engineer CiscoThalwil, Switzerland 15d Designing analog circuits and components for ASICs deployed across Cisco platforms, focusing on power, performance, and area goals.
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Senior SerDes & Analog Layout Design Engineer MicrosoftUnited States, North Carolina, Raleigh 15d Drive physical implementation of complex D2D SerDes and analog/mixed-signal IP in advanced process technologies, from floorplanning through tapeout, signoff, and integration.
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Package Design Staff/Sr.Staff Engineer MarvellBangalore 16d Develop advanced microelectronic packages (C4, BGA) for high-speed interfaces, driving development from concept through tapeout to ensure performance, reliability, and manufacturability.
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Staff Engineer, Hardware Design (PCB Layout)↗ CelesticaAustin, TX, US 16d Execute layout, routing, and component placement for high-density, multi-layer PCBs (12 to 28+ layers) in high-performance AI, data storage, networking, and server hardware.
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(Senior) System Engineer Photonic Integrated Circuits (m/f/x) ZeissgroupOberkochen, DE 16d Designing, developing, and validating integrated photonic systems and components to advance PIC technology for AI, communication, and sensor applications.
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Electrical Engineer FlirUS - Chestnut Ridge, NY $91k–$91k16d Design precision, high-speed, RF analog, and mixed-signal circuitry for next-generation probes and oscilloscope acquisition systems.
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?Experienced ASIC Analog Design Engineer (m/f/d) Deutschland 16d Designing analog and mixed-signal high-voltage integrated circuits for automotive sensor interfaces and smart power devices.
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?Experienced ASIC Analog Layout Engineer (m/f/d) Deutschland 16d Top-level integration of analog and mixed-signal ICs, driving layout development for robust, DRC-compliant designs with optimal area utilization.
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Senior Package Modeling Engineer NVIDIAUS, CA, Santa Clara $124k–$124k16d Conduct Finite Element Analysis (FEA) to assess stress, warpage, and thermo-mechanical behavior in advanced semiconductor packaging platforms.
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Package Development Engineer ON SemiconductorSan Jose, CA, United States $150k–$150k17d Lead the development and qualification of advanced multi-Phase Power Module, DrMOS, and Smart Power Stage (SPS) packages from concept through production release.
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Chip Package Signal and Power Integrity Engineer↗
GoogleSunnyvale, CA, US
$192k–$192k17d
Drive chip-package-system co-design by performing Signal Integrity (SI) and Power Integrity (PI) analysis and optimization for high-performance computing (HPC) based on 2.5D/3D package technology.
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