Analog IC Layout Designer
Core
Create transistor- and block-level layouts for Op-Amps, references, ADC/DACs, PLLs, sensor readout, and high-speed interfaces for CMOS image sensor applications.
Role type
Analog IC Layout Designer
Builds
High-performance analog and mixed-signal ICs for CMOS image sensor applications
Domain
Semiconductor / Analog IC Design
Required skills
Analog matching, parasitics, device physics, ESD, reliability, transistor-level schematic interpretation, advanced CMOS technologies, signoff, Cadence Virtuoso, Calibre, Assura
Preferred skills
CIS, ADC/DAC, PLL, high-voltage, low-noise sensor-interface, EM/IR, LDE, ESD/latch-up, advanced-node, tapeout
Technologies
Cadence Virtuoso, Calibre, Assura
Responsibilities
Create transistor- and block-level layouts, optimize floorplans for matching/area/noise/power/EM reliability, apply layout techniques (common-centroid, interdigitation, shielding), run DRC/LVS/ERC/density/fill verification, minimize parasitic coupling and layout-dependent effects, support parasitic extraction and post-layout simulation, collaborate with design/process/verification/CAD teams, contribute to layout reviews
Seniority
Mid-level, hands-on IC