IO and Mixed Signal Layout Design Engineer
Core
Design full custom layouts of I/O libraries and Analog Mixed Signal IP in planar and FinFET technologies.
Role type
Senior IC physical design engineer (analog/mixed-signal)
Builds
I/O libraries and Analog Mixed Signal IP blocks
Domain
Semiconductor physical design (analog/mixed-signal)
Required skills
I/O library design, Analog Mixed Signal IP development, Planar and FinFET layout, ESD and Latch-up principles, Cadence Virtuoso, Siemens CALIBRE, DRC/LVS/ANT/ERC/DFM verification, LEF generation, PnR flow
Preferred skills
AI and automation in layout, Script Programming, SKILL Programming
Technologies
Cadence Virtuoso, Siemens CALIBRE
Responsibilities
Design full custom layouts of I/O libraries and Analog Mixed Signal IP, Drive critical floor-planning decisions, Perform comprehensive layout verification, Complete ownership from end to end deliverables
Seniority
Mid-level, hands-on IC