ASIC Layout Engineer
Core
Design and verify standard cell layouts for next-generation ASICs on FinFET and GAA nodes, ensuring clean physical verification and library quality.
Role type
Senior IC ASIC Layout Engineer
Builds
Standard cell libraries (logic, high-drive, clock, level shifter, tap/boundary, specialty) for Cisco Silicon One platform switches and routers
Domain
Semiconductor / ASIC Design / Analog & Digital IC
Required skills
Standard cell layout design, Physical verification (DRC, LVS, antenna, ERC, extraction), Library QA (GDS, LEF, Liberty, NDM, CDL), Scripting (Python, Tcl, SKILL), Cadence Virtuoso proficiency
Preferred skills
Analog/mixed-signal layout (PLLs, LDOs, bandgaps, IOs, sensors), Characterization and Liberty modeling, EM/IR analysis, Low-power cell design (multi-Vt, power gating), Library release workflows
Technologies
Calibre, ICV, StarRC, Quantus, Cadence Virtuoso, PrimeLib, Liberate, SiliconSmart, Python, Tcl, SKILL, Perl
Responsibilities
Design standard cell layouts for logic, high-drive, clock, and specialty cells; Optimize layouts for density, performance, power, EM, and manufacturability; Run physical verification and fix issues for clean signoff; Develop and maintain automation scripts for layout and verification; Support analog/mixed-signal layout and characterization teams; Debug block-level layout and verification issues; Participate in layout reviews and methodology improvements
Seniority
Mid-Senior, hands-on IC
