Gate-level Noise (Signal Integrity) / STA CAD Engineer
Core
Architect and drive gate-level noise and static timing analysis (STA) methodologies to ensure signal integrity and robustness of Apple silicon across advanced technology nodes.
Role type
Senior IC Signal Integrity / STA CAD Engineer
Builds
Production CAD flows, noise/timing analysis infrastructure, and AI-agent workflows for large-scale SOC designs
Domain
Semiconductor / VLSI Design / Signal Integrity
Required skills
Gate-level noise analysis, Static Timing Analysis (STA), EM/SEB/thermal methodologies, Tcl/Perl/Python scripting, Root-cause analysis, Tool qualification, ECO methodology, AI-agent workflow integration
Preferred skills
Tempus, PrimeTime-SI, ETS/Celtic, SPICE simulation, LLM-based triage, Agentic diffing, Natural-language query over report corpora
Responsibilities
Define and architect noise/STA analysis methodology and tool qualification strategy; Own end-to-end flows and scripts for gate-level noise and STA; Conduct deep root-cause analysis of noise violations and timing anomalies; Serve as technical authority for design and Physical Design teams; Build infrastructure for large-scale noise/timing report mining and visualization; Develop noise/timing ECO methodology and custom scripts; Mentor junior engineers on noise/STA techniques
Seniority
Senior, hands-on IC
