Package Design Engineer – Principal Engineer
Core
Lead and develop the package design team to drive next-generation high-performance compute (HPC) package and system architecture for Qualcomm Datacenter, owning end-to-end strategy from concept through production.
Role type
Principal Engineer / Director of Engineering (Package Design)
Builds
Advanced 2.5D/3D integration packages, silicon interposers, bridges, and high-density substrates for AI, HPC, and server products.
Domain
Semiconductor packaging and system architecture
Required skills
Advanced semiconductor packaging (2.5D/3D, HBM, silicon interposers), chip-package-board co-design, SI/PI simulation, thermal-mechanical co-design, EDA tool expertise (Cadence APD/SiP, Siemens Xpedition), team leadership and hiring, foundry/OSAT ecosystem navigation, design-for-manufacturability, technology roadmap definition.
Preferred skills
Master's or Ph.D. in EE/ME/Materials Science, 15+ years of semiconductor packaging experience, proven record of leading large cross-functional engineering organizations.
Technologies
Cadence APD/SiP, Siemens Xpedition, XtractIM, PowerSI, HFSS, Q3D
Responsibilities
Provide technical and organizational leadership for the package design team; own end-to-end package architecture strategy; drive architecture selection for multi-die packages; lead chip-package-board co-design; partner with silicon, manufacturing, and supply-chain teams; guide physical design and verification; define electrical requirements for high-speed interfaces; drive thermal-mechanical co-design; establish scalable design methodologies; lead technical engagement with foundries and OSATs; develop technology roadmaps.
Seniority
Principal/Director, strategic leadership with hands-on technical credibility
