Design Engineer
Core
Custom layout floorplan, matching guides, resistor/capacitor placement, coupling & noise reduction, and routing for sensitive and mixed-signal signals.
Role type
Senior IC analog layout engineer (mixed-signal/PHY)
Builds
Custom layout top-level hierarchy floorplans for blocks and power networks
Domain
Semiconductor IC design, analog/mixed-signal
Required skills
Analog/custom layout design, DRC/LVS/ERC analysis, EMIR analysis, high-speed mixed-signal PHY design, Virtuoso XL, Pegasus/Calibre DRC/LVS, Voltus-FI
Preferred skills
PERC run experience, FinFET layout, ESD/Latch-up, digital P&R cooperation
Technologies
Virtuoso XL, Pegasus, Calibre, Voltus-FI
Responsibilities
Create custom layout floorplans and matching guides; place resistors and capacitors; route sensitive and mixed-signal signals; perform DRC/LVS/ERC and EMIR analysis; collaborate with analog circuit design teams.
Seniority
Mid-level, hands-on IC engineer
