Packaging Engineer
Core
Senior Package Design Engineer executing complex semiconductor package designs for high-performance computing solutions in data center and AI markets.
Role type
Senior IC packaging engineer (2.5D/3D integration)
Builds
Advanced packaging architectures (chiplets, interposers, substrate layouts) for AMD's high-performance computing products
Domain
Semiconductor manufacturing / Advanced packaging / HPC
Deliverable
production ML models
Required skills
End-to-end package design execution, Substrate layout design, Bump map design, Interposer design, 2.5D/3D integration, EDA tools (Cadence SIP/APD, Synopsys 3DICC), OSAT/foundry collaboration, Signal Integrity fundamentals, Power Integrity fundamentals
Preferred skills
AI/ML application in design workflows, Design methodology definition, Cross-functional technical leadership
Technologies
Cadence SIP, Cadence APD, Synopsys 3DICC
Responsibilities
Develop substrate layouts, bump maps, and interposer designs for advanced packaging; Drive design decisions through collaboration with SI/PI, mechanical, and SOC teams; Partner with OSATs and substrate suppliers to deliver optimized solutions; Define and enhance package design methodologies and flows
Seniority
Senior, hands-on IC
