Physical Design Engineer
Core
ASIC Block level physical design for GPU chips, covering floor planning, placement, clock tree synthesis, routing, timing closure, and physical verification.
Role type
Senior IC physical design engineer (GPU)
Builds
GPU ASIC blocks
Domain
Semiconductor / VLSI / GPU
Required skills
Floor planning, Placement, Clock Tree Synthesis, Routing, Static Timing Analysis, Physical Verification (DRC/LVS), Low-power techniques (clock gating, power gating), EMIR Analysis, Scripting (Perl, Shell, TCL, Python), MOS/VLSI fundamentals, RTL-to-GDS flow optimization
Preferred skills
N/A
Technologies
Innovus, IC Compiler, Primetime, Caliber, Voltus, Genus, DC Compiler
Responsibilities
Perform floor planning, macro placement, logic placement, and clock tree synthesis for GPU blocks; Execute routing and timing closure using static timing analysis tools; Conduct physical verification (DRC/LVS) and electrical analysis (EMIR, Voltus); Apply low-power design techniques; Write scripts to extract design data and analyze metrics; Collaborate with RTL teams for early feedback and optimization.
Seniority
Mid-level, hands-on IC
