Physical Design Engineer
Core
Drive physical design and timing closure for large complex SoC designs and core platforms, from RTL to GDS2 implementation.
Role type
Senior IC physical design engineer (SoC)
Builds
High-frequency, low-power integrated circuits and system-on-chip (SoC) platforms
Domain
Semiconductor / VLSI / Digital IC Design
Required skills
Floor planning, physical synthesis, place and route (P&R), timing closure, power optimization, netlist to GDS2 implementation, TCL/Perl/Python/Unix scripting, physical verification (Calibre), high-speed digital circuit analysis, clock optimization, ECO implementation
Preferred skills
N/A
Technologies
ICC, ICC2, Innovus, Calibre
Responsibilities
Complete netlist to GDS2 implementation for partitions meeting schedule and design goals; Be responsible for timing, physical & electrical verification, driving signoff closure; Resolve design and flow issues related to physical design; Be a focal point for place and route, setting goals and milestones; Drive frontend and backend implementation from RTL to gds2; Responsible for hands-on physical implementation and timing closure of core platforms and SoC's; Streamline timing signoff criterions and flows; Responsible for floor planning, physical synthesis, and physical design closure of large complex designs at 1GHz+ clock cycles; Drive physical design and timing convergence of high-frequency low-power at block, cluster, and/or full chip level.
Seniority
Senior, hands-on IC
