Front End Design Engineer
Core
Convert RTL designs into netlists, optimize power/performance/area, and ensure design robustness and correctness for chip development.
Role type
Senior IC digital design engineer (RTL synthesis & verification)
Builds
Digital logic circuits and microarchitectures for Apple products
Domain
Semiconductor hardware design
Required skills
RTL synthesis, Static Timing Analysis (STA), Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Lint checks, Unit testbench creation, Simulation waveform analysis, Verilog, SystemVerilog
Preferred skills
N/A
Technologies
Design Compiler, Genus, industry-standard RTL synthesis tools, simulation tools
Responsibilities
Convert RTL designs into netlists using synthesis tools; Optimize power, performance, and area via synthesis recipes; Perform CDC and RDC checks to ensure robustness; Perform logical equivalence checks and support ECO generation; Perform static timing analysis to identify critical paths and propose optimizations; Analyze RTL simulation waveforms to understand design intent; Perform lint checks to ensure RTL code quality.
Seniority
Mid-level, hands-on IC
