Camera Subsystem Integration Lead
Core
Lead the integration of Camera and Image Processing subsystems into next-generation SoCs, defining architecture, interfaces, and driving RTL integration across multiple IPs.
Role type
Senior IC ASIC Design and Subsystem Integration Engineer
Builds
Next-generation System on Chips (SoCs) with integrated Camera and Image Processing subsystems
Domain
Semiconductor / ASIC Design / SoC Integration
Required skills
Verilog/SystemVerilog RTL design and debugging, Complex ASIC/SoC subsystem integration, Design Verification methodologies, SoC bus/interconnect protocols (AHB, AXI), Clock/reset/interrupt/register/power-domain integration, RTL quality methodologies (lint, CDC/RDC, synthesis, timing analysis), Cross-functional team leadership
Preferred skills
Camera/Image Processing/Video/Multimedia/DSP hardware experience, ASIC implementation of Camera/Image Processing IP, High-bandwidth data paths/NoC/interconnects optimization, Low-power methodologies (UPF), Scripting (Python, Perl, Tcl), End-to-end subsystem flow (architecture to silicon bring-up)
Technologies
Verilog, SystemVerilog, AHB, AXI, UPF, Python, Perl, Tcl
Responsibilities
Own and drive Camera subsystem-level RTL integration across multiple IPs, Collaborate with hardware and system architects to define subsystem architecture and interfaces, Lead integration of new IPs, features, and SoC-facing interfaces, Own top-level integration of clocks, resets, power domains, registers, interrupts, buses, and configuration paths, Drive RTL baseline, integration, and release readiness, Run and review RTL quality checks (lint, CDC/RDC, low-power, connectivity, synthesis, timing), Partner with DV teams to define verification requirements and test scenarios, Lead debug of complex issues spanning multiple IPs and subsystem boundaries, Identify integration risks and drive cross-functional issues to closure, Drive integration methodology and automation improvements, Provide technical guidance and mentorship to engineers
Seniority
Senior, hands-on IC with technical leadership
