FE Engineer
Core
Define microarchitecture, design RTL in SystemVerilog/Verilog, and integrate/verify IP for high-speed communication systems.
Role type
Senior IC hardware design engineer (RTL/SOC)
Builds
High-speed communication IPs and SoC components
Domain
Semiconductor hardware design
Required skills
SystemVerilog, Verilog, RTL design, IP integration, CDC/RDC analysis, low-power design (clock gating, power gating, DVFS), high-speed interface design (AXI/AHB), synthesis tools (Synopsys, Cadence), scripting (Python, Perl, TCL), computer architecture, SoC design, wireless communication
Preferred skills
N/A
Technologies
SystemVerilog, Verilog, Python, Perl, TCL, Synopsys, Cadence, AXI, AHB
Responsibilities
Write RTL for high-speed communication IPs, perform IP integration and verification, run tools for lint-free and CDC-clean design, apply synthesis and timing constraints, collaborate with system/algorithm and firmware teams, implement low-power features
Seniority
Senior, hands-on IC
