Physical Design Engineer
Core
Drive physical aspects of complex digital logic blocks early in the design cycle, from floor planning to GDS2 implementation and sign-off.
Role type
Senior IC physical design engineer (digital logic)
Builds
Optimized chip layouts meeting schedule, design goals, and PPA targets
Domain
Semiconductor / VLSI physical design
Required skills
floor planning, macro placement, clock tree synthesis, static timing analysis (STA), power analysis (IR/IVD), physical verification (DRC/LVS), formal checking, TCL/Python scripting, Cadence Innovus, Synopsys ICC-2, Synopsys Primetime, Calibre, UPF, Voltus, Redhawk
Preferred skills
N/A
Technologies
Cadence Innovus, Synopsys ICC-2, Synopsys Primetime, Calibre, UPF, Voltus, Redhawk
Responsibilities
Conduct floor planning, pin assignments, macro placement, and iteration for optimized placement; Perform clock tree synthesis, optimization, routing, and post-route optimization; Complete netlist to GDS2 implementation; Perform setup, hold, transition, and static timing checks (STA); Run Static IR and Dynamic IVD analysis and power optimization; Execute formal checking, full chip timing closure, physical verification, and signoff checklist closure; Partner with CAD teams to develop new tools and methodologies; Evaluate and develop PD-centric flows to improve leakage, dynamic power, area, and performance; Work on top-level full chip Place & Route implementation and complex IP-level partitions.
Seniority
Senior, hands-on IC
