Physical Design Engineer
Core
Drive physical aspects of chip partitions early in the design cycle, completing netlist to GDS2 implementation and ensuring signoff closure.
Role type
Senior IC physical design engineer (SoC)
Builds
Integrated circuits (chips) for consumer electronics
Domain
Semiconductor / VLSI design
Required skills
Innovus, Fusion Compiler APR, static timing analysis, timing convergence, IR/IVD analysis, LVC/DRC debug, floorplanning, placement, clock tree synthesis, routing, ECO, power gating, clock gating, multi-voltage domain design, Tcl, Perl, Python
Technologies
Innovus, Fusion Compiler APR, 7nm technology nodes
Responsibilities
Understand partition architecture and drive physical aspects early in design cycle; Complete netlist to GDS2 implementation for partitions meeting schedule and design goals; Perform timing, physical & electrical verification and drive signoff closure; Resolve design and flow issues related to physical design and identify potential solutions.
Seniority
Senior, hands-on IC
