Physical Design Engineer
Core
Physical design implementation of partitions and top-level chips, including place and route flows, floor planning, and timing closure.
Role type
Senior IC physical design engineer (digital logic)
Builds
Complex digital logic blocks and full-chip implementations
Domain
Semiconductor / Digital IC design
Required skills
Cadence Innovus, Synopsys ICC-2, Synopsys Primetime-SI, Calibre (LVS/DRC), UPF, Conformal-LP, Voltus, Redhawk, TCL, Python, TCSH, Verilog, microprocessor system design, semiconductor device physics
Preferred skills
N/A
Technologies
Cadence Innovus, Synopsys ICC-2, Synopsys Primetime-SI, Calibre, UPF, Conformal-LP, Voltus, Redhawk, TCL, Python, TCSH, Verilog
Responsibilities
Implement physical design of partitions and top level; Develop and test place and route flows; Conduct floor planning, pin assignments, macro placement and evaluation of logic; Iterate over placement to get the optimized placement and timing; Perform clock tree synthesis, optimization, routing and post-route optimization; Conduct setup, hold, transition and other static timing checks and closure; Run Static Voltage Droop and dynamic Voltage Droop and other power related optimization and signoff; Conduct formal checking and signoff, full chip timing closure, physical verification and closure, and signoff checklist closure
Seniority
Senior, hands-on IC
