RTL Engineer – Physical AI Solutions
Core
Designing, implementing, and verifying high-performance digital logic (RTL) for FPGA and programmable hardware solutions that accelerate Physical AI workloads.
Role type
Senior IC RTL Engineer (FPGA/AI Acceleration)
Builds
FPGA-accelerated AI pipelines, real-time perception systems, robotics compute platforms, edge AI inferencing architectures
Domain
Semiconductor / FPGA / Physical AI / Computer Architecture
Deliverable
production ML models
Required skills
Verilog, SystemVerilog, Computer Architecture, Digital Design, ASIC/FPGA Methodologies, Simulation & Verification, Datapath Design, Control Logic, Synthesis, Static Timing Analysis
Preferred skills
AI/ML Accelerator Design, FPGA Architectures, EDA Tools (Synopsys/Cadence), High-bandwidth Memory/NoC/PCIe, Hardware-Software Co-design, Python/C++
Technologies
Verilog, SystemVerilog, FPGA, Synopsys, Siemens EDA, Cadence, Python, C/C++, PCIe, Ethernet, CXL
Responsibilities
Design RTL for FPGA solutions, translate specs to synthesizable code, create microarchitecture specs, optimize for PPA, collaborate on verification strategies, support synthesis/timing closure, debug RTL/simulation/silicon issues, contribute to feature definition
Seniority
Mid-Senior, hands-on IC
