Senior RTL Design Engineer – FPGA/ASIC Design
Core
Design, develop, integrate, and validate complex digital hardware solutions targeting FPGA and Adaptive SoC platforms, including RTL design, DSP algorithms, and system-level emulation.
Role type
Senior IC hardware design engineer (FPGA/ASIC)
Builds
High-performance FPGA and Adaptive SoC solutions for next-generation adaptive computing
Domain
Semiconductor / Hardware Design
Required skills
RTL design (VHDL/Verilog/SystemVerilog), FPGA design flows (synthesis, PnR, STA, timing closure), DSP algorithms, hardware-software co-design, system-level debugging, automation scripting (Python/Bash/Perl/Tcl), cross-functional collaboration
Preferred skills
AMD/Xilinx Vivado/Vitis, Versal Adaptive SoC, AI Engine programming, hardware acceleration, AXI protocols, SystemVerilog/UVM verification, embedded processors (ARM/MicroBlaze), board bring-up
Technologies
VHDL, Verilog, SystemVerilog, Python, Bash, Perl, Tcl, Vivado, Vitis, MATLAB, Linux, UVM
Responsibilities
Develop and optimize RTL designs; Contribute to FPGA implementation and timing closure; Develop DSP algorithms and hardware acceleration; Participate in hardware-software co-design; Maintain simulation and emulation environments; Perform system-level debugging and root-cause analysis; Collaborate with architecture, verification, and software teams
Seniority
Senior, hands-on IC
