Senior/Lead VLS Engineer - Global Circuits
Core
Architect and design custom ultra-low-jitter, low-skew clock distribution networks and power integrity solutions for advanced AI accelerator chips.
Role type
Senior/Lead VLSI Design Engineer (Analog/Mixed-Signal)
Builds
Custom clock networks, IO/ESD/Latch-Up structures, and power distribution systems for SambaNova RDU chips.
Domain
Semiconductor / AI Infrastructure / Advanced Process Nodes (7nm-2nm)
Deliverable
production ML models
Required skills
Custom analog/mixed-signal VLSI design, Clock Tree Synthesis (CTS), Signal Integrity (SI) analysis, Power Integrity (PI) analysis, ESD/Latch-Up design, Transistor-level circuit simulation, Physical layout optimization, Foundry design rule compliance
Preferred skills
Silicon reliability expertise, AI-assisted workflow automation (Python/TCL/SKILL), Top-level silicon integration leadership
Technologies
FinFET/GAA processes, PERC tools, EM/IR analysis tools, Parasitic extraction tools
Responsibilities
Design and optimize custom clock distribution networks (H-trees, grids, meshes), Perform comprehensive SI/PI/jitter/skew analysis, Develop low-power design methodologies, Collaborate on floor-planning and custom routing, Integrate custom IO pads and ESD clamps, Drive pre-silicon reliability sign-off and post-silicon bring-up support
