Physical Design Engineer
Core
Contribute to all phases of physical design for high-performance PHYs from RTL to GDSII delivery, focusing on timing, power, and area optimization.
Role type
Senior IC physical design engineer (PHY)
Builds
High-performance PHY chips and blocks
Domain
Semiconductor / Analog IC design
Deliverable
production ML models
Required skills
Static timing analysis, floorplanning, place and route, clock network design, ECO generation, LVS/DRC/ERC verification, Tcl/Perl/Python scripting, PPA optimization, EMIR analysis, low-power techniques (clock gating, power gating), ML algorithms for data mining, Cadence/Virtuoso tools
Responsibilities
Generate block/chip level static timing constraints, Build full chip floor-plan including pin placement, partitions and power grid, Develop and validate high performance low power clock network guidelines, Perform block level place and route and close the design to meet timing, area and power constraints, Generate and implement ECOs to fix timing, noise and EM IR violations, Run Physical Design verification flow at chip/block level and provide guidelines for other designers to fix LVS/DRC violations
Seniority
Senior, hands-on IC
