STA Engineer
Core
Lead timing closure and verification for Apple SoC chips in deep sub-micron technologies for high-end mobile applications.
Role type
Senior IC STA Engineer (ASIC)
Builds
High-quality IP deliverables and full System-on-Chip (SoC) designs
Domain
Semiconductor / ASIC Design / Mobile SoC
Required skills
Timing closure methodology, Full chip and block level timing analysis, Constraint generation and analysis, Scripting (TCL, Perl), ASIC design timing concepts, Synthesis and Logic equivalence checks, Signal integrity analysis
Preferred skills
Primetime tool proficiency, Synopsys GCA usage, Knowledge of timing corners/modes and process variations, Digital design fundamentals
Technologies
Primetime, Synopsys GCA, TCL, Perl, Synthesis tools, Logic equivalence checkers
Responsibilities
Own full chip and block level timing closure throughout the project lifecycle, Develop and maintain timing verification flows, Generate block and full chip timing constraints, Resolve complex timing issues for major SoC building blocks
Seniority
Mid-Senior, hands-on IC