Sr Principal Design Engineer
Core
Manage a Memory Controller Design Verification (DV) group focusing on MDV verification, including constrained random functional verification, formal property verification, and project execution.
Role type
Senior Individual Contributor / Team Lead Design Verification Engineer
Builds
Functional verification environments and test plans for memory controllers (DDR, PCIe, UCIe, USB)
Domain
Semiconductor / Electronic Design Automation (EDA) / Memory Controllers
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Constrained Random Functional Verification, Formal Property Verification, UVM methodology, Verilog, SystemVerilog, Team Management, Verification Strategy, Test Plan Generation
Preferred skills
AXI, CHI, DDR, PCIe, UCIe, USB, Memory Controller Verification
Technologies
UVM, Verilog, SystemVerilog, AXI, CHI
Responsibilities
Manage Memory Controller DV group and mentor junior engineers; Architect verification environments and define verification strategies; Lead interactions with RTL, Subsystem, and Performance teams; Review project signoff and quality of DDR controller feature verification; Engage in pre and post-sales customer interactions.
Seniority
Senior, hands-on IC with team leadership
