<Data center>DFT senior engineer
Core
Define and implement DFT architectures for data center ASIC products to ensure robust test solutions, yield improvement, and quality for mass production.
Role type
Senior IC DFT engineer (ASIC)
Builds
Data center ASIC chips
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture definition, test strategy development, RTL and gate-level DFT integration, ATPG, fault simulation, coverage analysis, silicon bring-up and debug, failure and yield analysis, pattern generation validation
Preferred skills
IR convergence support, DPPM improvement
Technologies
RTL, gate-level, ATPG tools, fault simulation tools
Responsibilities
Develop and optimize test strategies to achieve coverage and manufacturing goals; Integrate DFT features at RTL and gate-level; Perform ATPG, fault simulation, and coverage analysis; Collaborate with BE and PD teams to ensure DFT-friendly timing; Lead silicon bring-up and debug of test features; Work with product teams to facilitate pattern generation and validation
Seniority
Senior, hands-on IC
